1. Field of the Invention
The present invention relates to an ECL (Emitter Coupled Logic) circuit which requires high-speed operation and low power consumption.
2. Description of the Related Art
In the prior art (FIG. 1), the rising speed of an output waveform is determined by the current flow from the emitter follower of an output transistor. On the other hand, the falling speed is determined by the discharging of charges in a load capacitor C.sub.L through a resistor R.sub.EF connected to the emitter of the output transistor. To increase the speed, therefore, the value of the resistor R.sub.EF has only to be reduced. However, this undesirably increases the current consumption. The prior art cannot therefore increase the falling speed of the output without increasing the power dissipation.
According to the structure as disclosed in U.S. Pat. Nos. 4,629,913, 4,539,493, 4,687,953, 4,835,420, the output stage is designed to have a totem pole structure with the upper transistors constituting a conventional emitter follower and the lower transistor forming a differential waveform using the capacitor C, so that operating this lower transistor at the falling time of the output discharges the charges from the load capacitor C.sub.L. This arrangement can improve the falling speed of the output by increasing the capacitance of the capacitor C. Increasing the capacitance of the capacitor, however, increases the area of the capacitor, which will hinder circuit integration and thus result in design restriction.